Set Fully Associtive Cache with LRU

I need to change CacheMemory.hh to enable fully associtive cache with LRU in Rocks.

ale-01% hg diff CacheMemory.hh


diff -r 971902a8740e src/mem/ruby/system/CacheMemory.hh
--- a/src/mem/ruby/system/CacheMemory.hh Tue Oct 20 15:29:02 2009 -0500
+++ b/src/mem/ruby/system/CacheMemory.hh Mon Feb 22 20:42:01 2010 -0600
@@ -218,8 +218,19 @@
}
}

+
+
m_cache_num_sets = cache_size / m_cache_assoc;
- m_cache_num_set_bits = log_int(m_cache_num_sets);
+ if(m_cache_assoc > cache_size) {
+ // this is for full assoc
+ m_cache_num_set_bits = 0;
+ m_cache_num_sets = 1;
+ } else {
+ m_cache_num_set_bits = log_int(m_cache_num_sets);
+ }
+

if(policy == "PSEUDO_LRU")
m_replacementPolicy_ptr = new PseudoLRUPolicy(m_cache_num_sets, m_cache_assoc);
@@ -277,7 +288,18 @@
Index CacheMemory::addressToCacheSet(const Address& address) const
{
assert(address == line_address(address));
- return address.bitSelect(RubySystem::getBlockSizeBits(), RubySystem::getBlockSizeBits() + m_cache_num_set_bits-1);
+ if(m_cache_num_set_bits > 0 ) {
+ return address.bitSelect(RubySystem::getBlockSizeBits(), RubySystem::getBlockSizeBits() + m_cache_num_set_bits-1);
+ } else if(m_cache_num_set_bits == 0 ) {
+ // This is the case that not cache set bit is used
+ // Because this is the fully assoicitive cache
+ //return address.bitSelect(RubySystem::getBlockSizeBits(), RubySystem::getBlockSizeBits() + m_cache_num_set_bits);
+ return 0;
+ } else {
+ // there is something wrong here that m_cache_num_set_bits is less than 0 ?!
+ assert(1!=0);
+ return -1;
+ }
}