LogTM L1 cache

bool Sequencer::doRequest(const CacheMsg& request) function contains the code for deciding whether the current memory operation hits in the L1 cache--referred to as fastpath. If a memory operation hits in the L1 cache, then there is no needs for the memory operation to go to the protocol level of the LogTM, which means the latency will be 1 for that memory operation.

It is ,however, necessary for some memory operations to go to the protocol to make our simulation more accurate. There situations then must be coded in the bool Sequencer::doRequest(const CacheMsg& request) function to force the simulator to go the protocol level.