Simics Processor

SimicsProcessor::makeRequest is the function in SimicsProcessor.C that add a CacheRequestType_LOG_ST to the execution queue if the current instruction is a store. And in this system, the Log write is done with appropriate penalty.

This means that Log write is handled by the system if the target write is visible to the protocol. For the target write to be visible to the protocol, it has to miss in the L1 because if the target write hits in the L1, the Log write is handled in the Sequencer::doRequest function. When handled in the Sequencer::doRequest function, the Log write is not penalized appropriately.